Rising complexity and performances of embedded systems, shortening time-to-ma- rket demands for digital equipments, growing installed bases of intellectual properties, stress high-level design as a prominent research topic to compensate a widening productivity gap. In this aim, we put the principles of polychronous design (i.e. multi-clocked and synchronous) to work in the context of the real-time Java programming language by introducing a method for modeling, transforming, verifying and simulating multi-threaded real-time Java components in the multi-clocked synchronous data-flow design language Signal. We put this technique to work for the component-based design and refinement of an even-parity checker with communication protocols.