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CASH: Revisiting hardware sharing in single-chip parallel processor

Romain Dolbeau 1 André Seznec 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : As the increasing of issue width has diminishing returns with superscalar processor, thread parallelism with a single chip is becoming a reality. In the past few years, both SMT (Simultaneous MultiThreading) and CMP (Chip MultiProcessor) approaches were first investigated by academics and are now implemented by the industry. In some sense, CMP and SMT represent two extreme design points. In this paper, we propose to explore possible intermediate design points for on-chip thread parallelism in terms of design complexity and hardware sharing. We introduce the CASH parallel processor (for CMP And SMT Hybrid). CASH retains resource sharing a la SMT when such a sharing can be made non-critical for implementation, but resource splitting a la CMP whenever resource sharing leads to a superlinear increase of the implementation hardware complexity. For instance, sparsely used functional units (e.g. dividers), but also branch predictors and instruction and data caches, can be shared among several «processor» cores. CASH does not exploit the complete dynamic sharing of resources enabled on SMT. But it outperforms a similar CMP on a multiprogrammed workload, as well as on a uniprocess workload. Our CASH architecture shows that there exists intermediate design points between CMP and SMT.
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https://hal.inria.fr/inria-00071925
Contributor : Rapport de Recherche Inria <>
Submitted on : Tuesday, May 23, 2006 - 7:16:52 PM
Last modification on : Thursday, January 7, 2021 - 4:29:00 PM
Long-term archiving on: : Sunday, April 4, 2010 - 10:44:54 PM

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  • HAL Id : inria-00071925, version 1

Citation

Romain Dolbeau, André Seznec. CASH: Revisiting hardware sharing in single-chip parallel processor. [Research Report] RR-4660, INRIA. 2002. ⟨inria-00071925⟩

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