High Throughput Implementations of the RC6 Block Cipher Using Virtex-E and Virtex-II Devices

Jean-Luc Beuchat 1
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : This short paper is devoted to the study of effective hardware architectures for the RC6 block cipher using Virtex-E and Virtex-II FPGA devices. The key point of the implementation is the design of an arithmetic operator computing f(X)=(X(2X+1))2^w. Significant speed and area improvements are obtained by taking full advantage of the small multiplier blocks available in Virtex-II devices.
Document type :
Reports
Complete list of metadatas

https://hal.inria.fr/inria-00072093
Contributor : Rapport de Recherche Inria <>
Submitted on : Tuesday, May 23, 2006 - 7:46:27 PM
Last modification on : Thursday, February 7, 2019 - 4:47:14 PM
Long-term archiving on : Sunday, April 4, 2010 - 10:52:49 PM

Identifiers

  • HAL Id : inria-00072093, version 1

Collections

Citation

Jean-Luc Beuchat. High Throughput Implementations of the RC6 Block Cipher Using Virtex-E and Virtex-II Devices. RR-4495, INRIA. 2002. ⟨inria-00072093⟩

Share

Metrics

Record views

168

Files downloads

312