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Advances in Bit Width Selection Methodology

David Cachera 1 Tanguy Risset 1
1 COSI - Codesign of Silicon Systems
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : We describe a method for the formal determination of signal bit width in fixed points VLSI implementations of signal processing algorithms containin- g loop nests. The main advance of this paper lies in the fact that we use results of the (max,+) algebraic theory to find the integral bit width of algorithms containing loop nests whose bound parameters are not statically known. Combined with recent results on fractional bit width determination, the results of this paper can be used for 1-dimensional systolic-like arrays implementing linear signal processing algorithms. Although they are presented in the context of a specific high level design methodology (based on systems of affine recurrence equations), the results of this work can be used in many high level design environments.
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Submitted on : Tuesday, May 23, 2006 - 7:53:07 PM
Last modification on : Friday, February 4, 2022 - 3:23:02 AM
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  • HAL Id : inria-00072136, version 1


David Cachera, Tanguy Risset. Advances in Bit Width Selection Methodology. [Research Report] RR-4452, INRIA. 2002. ⟨inria-00072136⟩



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