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Fast Redundancy Elimination Using High-Level Structural Information from Esterel

Dumitru Potop-Butucaru 1
1 TICK - Theory and Practice of Synchronous Reactive Systems
CRISAM - Inria Sophia Antipolis - Méditerranée , MINES ParisTech - École nationale supérieure des mines de Paris
Abstract : Esterel programs and SyncCharts hierarchical automata are compiled into flat sequential circuits. The current compiling process often generates too many latches and gates. We propose a compositional technique based on structural information that efficiently removes redundant latches and gates, without adding extra logic. The transformation works in linear time and gives good practical results. The simplified circuit can be used for simulation, verification, and optimisation.
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Submitted on : Tuesday, May 23, 2006 - 8:14:24 PM
Last modification on : Friday, February 4, 2022 - 3:11:22 AM
Long-term archiving on: : Sunday, April 4, 2010 - 11:00:57 PM


  • HAL Id : inria-00072257, version 1


Dumitru Potop-Butucaru. Fast Redundancy Elimination Using High-Level Structural Information from Esterel. RR-4330, INRIA. 2001. ⟨inria-00072257⟩



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