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On digit-recurrence division algorithms for self-timed circuits

Nicolas Boullis 1 Arnaud Tisserand 1
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : The optimization of algorithms for self-timed or asynchronous circuits requires specific solutions. Due to the variable-time capabilities of asynchronous circuits, the average computation time should be optimized and not only the worst case of the signal propagation. If efficient algorithms and implementations are known for asynchronous addition and multiplication, only straightforward algorithms have been studied for division. This paper compares several digit-recurrence division algorithms (speed, area and circuit activity for estimating the power consumption). The comparison is based on simulations of the different operators described at the gate level. This work shows that the best solutions for asynchronous circuits are quite different from those used in synchronous circuits.
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Submitted on : Wednesday, May 24, 2006 - 9:51:16 AM
Last modification on : Friday, February 4, 2022 - 3:16:02 AM
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  • HAL Id : inria-00072398, version 1



Nicolas Boullis, Arnaud Tisserand. On digit-recurrence division algorithms for self-timed circuits. [Research Report] RR-4221, INRIA. 2001. ⟨inria-00072398⟩



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