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Further Reducing the Redundancy of a Notation over a Minimally Redundant Digit Set

Marc Daumas 1 David W. Matula
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Redundant notations are used implicitly or explicitly in many digital designs. They have been studied in details and a general framework is known to reduce the redundancy of a notation down to the minimally redundant digit set. We present here an operator to further reduce the redundancy of such a representation. It does not reduce the number of allowed digits since removing one digit to a minimally redundant digit set is a conversion to a non redundant digit set and this is an expensive operation. Our operator introduces some correlation between the digits to reduce the number of possible redundant notations for any represented number. This reduction is visible in small useful operators like the elimination of leading zeros. We also present a key application with a CMOS Booth recoded multiplier. Our multiplier is able to accept both a redundant or a non redundant input with very little modifications and almost no penalty in time or space compared to state-of-the-art non redundant multipliers.
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Submitted on : Wednesday, May 24, 2006 - 10:50:46 AM
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Marc Daumas, David W. Matula. Further Reducing the Redundancy of a Notation over a Minimally Redundant Digit Set. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Springer, 2003, 33 (1-2), pp.7-18. ⟨10.1023/A:1021133616373⟩. ⟨inria-00072767⟩



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