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Flexible Issue Slot Assignment for VLIW Architectures

Zbigniew Chamski 1 Christine Eisenbeis 1 Erven Rohou
1 A3 - Advanced analysis to code optimization
UP11 - Université Paris-Sud - Paris 11, Inria Saclay - Ile de France
Abstract : Programming specialized processors requires solving complex resource constrain- ts related to the underlying architecture. Although one instruction of the Philips TriMedia VLIW processor can issue five parallel operations, each category of operations can only be allocated to a subset of the five available slots. In this report we show how these restrictions can be translated into constraints based on reservation tables. This allows us to directly apply all classical algorithms for code generation and optimizatio- n. An important byproduct is that dynamic processes, such as «on the fly» code generation, are made tractable, even though resource constraints are strongly static.
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https://hal.inria.fr/inria-00072876
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Submitted on : Wednesday, May 24, 2006 - 11:09:39 AM
Last modification on : Friday, January 21, 2022 - 4:04:20 AM
Long-term archiving on: : Sunday, April 4, 2010 - 11:26:02 PM

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  • HAL Id : inria-00072876, version 1

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Zbigniew Chamski, Christine Eisenbeis, Erven Rohou. Flexible Issue Slot Assignment for VLIW Architectures. [Research Report] RR-3784, INRIA. 1999. ⟨inria-00072876⟩

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