Towards Portable Hierarchical Placement for FPGAs

Florent de Dinechin 1, 2 Wayne Luk 1, 2 Steve Mckeever 1, 2
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Field Programmable Gate Arrays (FPGAs) are usually programmed using languages and methods inherited from the domain of VLSI synthesis. These methods, however, have not always been adapted to the new possibilities opened by FPGAs, nor to the new constraints they impose on a design. This paper addresses in particular the issue of laying out the various components of an architecture on an FPGA. The problem is to embed placement information in FPGA-oriented hardware description languages, in a way that is both expressive enough to be useful, and abstract enough to be portable from one FPGA architecture to the other. A generic placement framework is defined to address this problem, and two prototype implementations of this framework are presented, for Xilinx 6200 and Xilinx 4000 devices, on the example of a bit-serial complex multiplier.
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https://hal.inria.fr/inria-00072885
Contributor : Rapport de Recherche Inria <>
Submitted on : Wednesday, May 24, 2006 - 11:10:39 AM
Last modification on : Wednesday, May 15, 2019 - 4:48:50 PM

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  • HAL Id : inria-00072885, version 1

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Florent de Dinechin, Wayne Luk, Steve Mckeever. Towards Portable Hierarchical Placement for FPGAs. [Research Report] RR-3776, LIP RR-1999-50, INRIA, LIP. 1999. ⟨inria-00072885⟩

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