Alternative Schemes for High-Bandwidth Instruction Fetching

Pierre Michaud 1 André Seznec 1 Stéphan Jourdan 2 Pascal Sainrat 3
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : Future processors combining out-of-order execution with aggressive speculation techniques will need to fetch multiple non-consecutive instruction blocks in a single cycle to achieve high-performance. Several high-bandwidth instruction fetching schemes have been proposed in the past few years. The Two-Block Ahead (TBA) branch predictor predicts two non-consecutive instruction blocks per cycle while relying on a conventional instruction cache. The trace cache (TC) records traces of instructions and delivers multiple non-consecutive instruction blocks to the execution core. The aim of this paper is to investigate the pros and cons of both approaches. Maintaining consistency between memory and TC is not a straightforward issue. We propose a simple hardware scheme to maintain consistency at a reasonable performance loss (1 to 5%). We also introduce a new fill unit heuristic for TC, the mispredict hint, that leads to significantly better performance (up to 20 %). This is mainly due to better prediction accuracy results and TC miss ratios. TBA requires double-ported or bank-interleaved structures to supply two non-consecutive blocks in a single cycle. We show that a 4-way interleaving scheme is cost-effective since it impairs performance by only 3 to 5%. Finally, simulation results show that such an enhanced TC scheme delivers higher performance than TBA when caches are large, due to a lower branch misprediction penalty and a higher instruction bandwidth on mispredictions. When the hardware budget is smaller, TBA outperforms TC because of a higher TC miss ratio and branch misprediction rate.
Type de document :
[Research Report] RR-3392, INRIA. 1998
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Soumis le : mercredi 24 mai 2006 - 12:28:27
Dernière modification le : vendredi 16 novembre 2018 - 01:23:55
Document(s) archivé(s) le : dimanche 4 avril 2010 - 23:41:22



  • HAL Id : inria-00073297, version 1


Pierre Michaud, André Seznec, Stéphan Jourdan, Pascal Sainrat. Alternative Schemes for High-Bandwidth Instruction Fetching. [Research Report] RR-3392, INRIA. 1998. 〈inria-00073297〉



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