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Latch Optimization in Circuits Generated from High-level Descriptions

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https://hal.inria.fr/inria-00073756
Contributor : Rapport de Recherche Inria <>
Submitted on : Wednesday, May 24, 2006 - 1:41:35 PM
Last modification on : Tuesday, September 15, 2020 - 4:58:04 PM
Long-term archiving on: : Sunday, April 4, 2010 - 11:57:09 PM

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  • HAL Id : inria-00073756, version 1

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Ellen M. Sentovich, Horia Toma, Gérard Berry. Latch Optimization in Circuits Generated from High-level Descriptions. RR-2943, INRIA. 1996. ⟨inria-00073756⟩

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