Branch Prediction and Simultaneous Multithreading

Sébastien Hily 1 André Seznec 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : In this paper, we examined the behavior of three of the best performing branch prediction strategies while executing several threads of instructions simultaneously. We studied the impact of the addition of one Return Address Stack per hardware context. We showed that a 12-deep stack per thread is sufficient to enhance greatly the accuracy of branch prediction while adding a minimal implementation cost.We explored the behavior of the branch predictors when independant applications are running simultaneously and when the workload is constituted by a parallel program. Our simulations showed that in multiprogramming environment, if the sizes of the tables (PHT/BTB) are proportionnal to the number of active threads, there are very few interactions, be they destructive or constructive. With parallel workloads, we could have expected a beneficial sharing effect. In fact, it is very dependant of the branch predictors and in the best case, the gains stay very limited. Finally we showed that, for the three predictors, whether in multiprogramming or in parallel processing, if the sizes of the tables are kept small, there is a slight increase of the mispredictions, which is mostly due to an increase of the conflicts in the BTB.
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Rapport
[Research Report] RR-2843, INRIA. 1996
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https://hal.inria.fr/inria-00073847
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Soumis le : mercredi 24 mai 2006 - 13:54:10
Dernière modification le : mercredi 16 mai 2018 - 11:23:02
Document(s) archivé(s) le : dimanche 4 avril 2010 - 23:59:54

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  • HAL Id : inria-00073847, version 1

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Sébastien Hily, André Seznec. Branch Prediction and Simultaneous Multithreading. [Research Report] RR-2843, INRIA. 1996. 〈inria-00073847〉

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