Multiple-Block Ahead Branch Predictors

André Seznec 1 Stéphan Jourdan 2 Pascal Sainrat 2 Pierre Michaud 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. To overcome the instruction fetch bottleneck shown in wide-dispatch «brainiac» processors, this paper presents a novel cost-effective mechanism called the multiple-block ahead branch predictor that predicts in an efficient way addresses of multiple basic blocks in a single cycle. Moreover and unlike the previous multiple predictor schemes, the multiple-block ahead branch predictor can use any of the branch prediction schemes to perform very accurate predictions required to achieve high-performance on superscalar processors. Finally, we show that pipelining the branch prediction process can be done by means of our predictor for «speed demon» processors to achieve higher clock rate.
Type de document :
[Research Report] RR-2825, INRIA. 1996
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Soumis le : mercredi 24 mai 2006 - 13:56:50
Dernière modification le : mercredi 23 mai 2018 - 17:58:06
Document(s) archivé(s) le : dimanche 4 avril 2010 - 21:13:06



  • HAL Id : inria-00073867, version 1


André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud. Multiple-Block Ahead Branch Predictors. [Research Report] RR-2825, INRIA. 1996. 〈inria-00073867〉



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