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Multiple-Block Ahead Branch Predictors

André Seznec 1 Stéphan Jourdan 2 Pascal Sainrat 3 Pierre Michaud 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. To overcome the instruction fetch bottleneck shown in wide-dispatch «brainiac» processors, this paper presents a novel cost-effective mechanism called the multiple-block ahead branch predictor that predicts in an efficient way addresses of multiple basic blocks in a single cycle. Moreover and unlike the previous multiple predictor schemes, the multiple-block ahead branch predictor can use any of the branch prediction schemes to perform very accurate predictions required to achieve high-performance on superscalar processors. Finally, we show that pipelining the branch prediction process can be done by means of our predictor for «speed demon» processors to achieve higher clock rate.
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https://hal.inria.fr/inria-00073867
Contributor : Rapport de Recherche Inria <>
Submitted on : Wednesday, May 24, 2006 - 1:56:50 PM
Last modification on : Thursday, March 18, 2021 - 2:32:25 PM
Long-term archiving on: : Sunday, April 4, 2010 - 9:13:06 PM

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  • HAL Id : inria-00073867, version 1

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André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud. Multiple-Block Ahead Branch Predictors. [Research Report] RR-2825, INRIA. 1996. ⟨inria-00073867⟩

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