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Optimal Loop Parallelization under Register Constraints

Christine Eisenbeis 1 Antoine Sawaya 1
1 A3 - Advanced analysis to code optimization
UP11 - Université Paris-Sud - Paris 11, Inria Saclay - Ile de France
Abstract : This report deals with the interaction between instruction scheduling and register allocation, in the case of straight line code and in the case of loops. This problem is at the heart of code optimization in microprocessors with instruction-level parallelism. Usual solutions use heuristics based on a decoupled approach. We propose here a formulation by linear integer programming, that allows dependence, resource and register constraints to be integrated in the same framework . By varying the parameters, all kinds of optimization problems can be solved exactly (maximization of the throughput, minimization of the number of registers). We report on examples of computation timings that turn out to be prohibitive in some specific cases, but tractable on average.
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https://hal.inria.fr/inria-00073911
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Submitted on : Wednesday, May 24, 2006 - 2:03:20 PM
Last modification on : Wednesday, September 16, 2020 - 4:57:22 PM
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  • HAL Id : inria-00073911, version 1

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Christine Eisenbeis, Antoine Sawaya. Optimal Loop Parallelization under Register Constraints. [Research Report] RR-2781, INRIA. 1996. ⟨inria-00073911⟩

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