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VSDF : Synchronous Data Flow for VLSI

Alain Kerihuel 1 Roderick Mcconnell 1 Sanjay Rajopadhye 1
1 API - Parallel VLSI Architectures
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : This article describes a modified Synchronous Data Flow model which is suitable for modeling synchronous VLSI circuits. The target model takes advantage of the synchronous nature of the operations to eliminate buffering between circuits where possible. We introduce a temporal notation, and define functions relevant to constructing a system.
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Submitted on : Wednesday, May 24, 2006 - 3:05:54 PM
Last modification on : Friday, February 4, 2022 - 3:15:33 AM
Long-term archiving on: : Sunday, April 4, 2010 - 10:15:46 PM


  • HAL Id : inria-00074339, version 1


Alain Kerihuel, Roderick Mcconnell, Sanjay Rajopadhye. VSDF : Synchronous Data Flow for VLSI. [Research Report] RR-2337, INRIA. 1994. ⟨inria-00074339⟩



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