Out-of-order execution of interruptible codes

Yvon Jégou 1
1 CALCPAR - Calculateurs Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : The superscalar execution model extracts independent instructions from a restricted window. When pipeline latencies go beyond some limit, out-of-order execution becomes necessary to fully exploit the independency of instructions. On the other hand, multithreading merges the execution of independent instruction flows. The simultaneous use of these two techniques is expected to produce a high degree of concurrent activities in fiture processors. But, the codes must be interruptible and restartable. Classical program state construction is incompatible with out-of-order of execution. In this paper, we present a new processor architecture which basic execution model is out-of-order execution. In this new model, the state of some execution does not correspond to a possible sequential state any more it represents the operations that remain to be executed. When the instruction flow is interrupted, a code sequence which contains the instructions that have been issued but which execution cannot be completed is built. On restart, the execution of this sequence restores the initial state.
Type de document :
[Research Report] RR-2139, INRIA. 1993
Liste complète des métadonnées

Contributeur : Rapport de Recherche Inria <>
Soumis le : mercredi 24 mai 2006 - 15:41:48
Dernière modification le : mercredi 16 mai 2018 - 11:23:14
Document(s) archivé(s) le : dimanche 4 avril 2010 - 22:19:30



  • HAL Id : inria-00074533, version 1


Yvon Jégou. Out-of-order execution of interruptible codes. [Research Report] RR-2139, INRIA. 1993. 〈inria-00074533〉



Consultations de la notice


Téléchargements de fichiers