Interleaved sectored caches: reconciling low tag volume and low miss ratio

André Seznec 1
1 CALCPAR - Calculateurs Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : Sectored caches have been used for many years in order to reduce the tag volume needed in a cache. In a sectored cache, a single address tag is associated with a sector consisting in several cache lines, while validity, dirty and coherency tags are associated with each of the inner cache lines. Using a sectored cache is a design trade-off between a low volume for cache tags allowed by a large line size and a low memory traffic induced by using a small line size. This technique has been used in many cache designs including small on-chip microprocessor caches and large external second level caches. Unfortunately on a sectored cache, a large part of the cache space may be wasted by invalid cache lines, then the miss ratio on a sectored cache is often significantly higher than the miss ratio on a non-sectored cache. Usually in a cache, a cache line location is statically linked to one and only one address tag word location. In the interleaved sectored cache we propose in this paper, this monolithic association is broken, the address tag location associated with a cache line location is dynamically chosen at fetch time among svereal possible locations. Trace driven simulations show that the hit ratio on an interleaved sectored cache is very close to the hit ratio on a non-sectored cache while the tag volume is very low as on traditional sectored caches.
Type de document :
Rapport
[Research Report] RR-2084, INRIA. 1993
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https://hal.inria.fr/inria-00074588
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Soumis le : mercredi 24 mai 2006 - 15:51:23
Dernière modification le : mercredi 16 mai 2018 - 11:23:14
Document(s) archivé(s) le : lundi 5 avril 2010 - 00:11:50

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André Seznec. Interleaved sectored caches: reconciling low tag volume and low miss ratio. [Research Report] RR-2084, INRIA. 1993. 〈inria-00074588〉

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