In a microprocessor, the cache hit time generally determines the clock frequency. But for the ten last years, a technological trend is the increaseof the cache miss penalty in terms of instruction issue delays, then maintaining the cache miss ratio as low as possible is also of particular interest. For a few years, there has been numerous studies focusing on a low cache hit time while maintaining low cache miss ratio. Unfortunately most of the proposed solutions implicitly suppose that the cache is virtually indexed. When using virtually indexed caches, the operating system (or may be some specific hardware) has to manage the consistency of caches and memory. In this paper, we propose the Direct-mapped Access Set-associative Check cache (DASC) for addressing both difficulties. On a DASC cache, the cache array is direct-mapped then the cache hit time is low, but as the tag array is set-associative, the external miss ratio is the same as the miss ratio of a set- associative cache. When the size of an associativity degree of the tag array is tied to the minimum page size, a virtually indexed DASC cache correctly handles all difficulties associated with cache consistency. Trace driven simulations show that, for cache sizes in the range of 16-32 Kbytes and for current minimum page size in the range 4-8 Kbytes, using a DASC cache is a valuable trade-off because it allows fast cache hit time and low cache miss ratio while cache consistency management is performed by hardware.