An integrated 2D systolic array for spelling correction

Dominique Lavenier 1
1 API - Parallel VLSI Architectures
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : This paper presents a fully integrated spelling co-processor for speeding up the character string comparison process. The chip we present is architectured around a banded 2-D systolic array consisting of 69 processors and is able to process more than 2 million of words per second. The high regularity of the chip has been exploited for investigating a design methodology based on the automated generation of a representative subcircuit : the kernel.
Type de document :
[Research Report] RR-1987, INRIA. 1993
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Soumis le : mercredi 24 mai 2006 - 16:05:22
Dernière modification le : mercredi 16 mai 2018 - 11:23:02
Document(s) archivé(s) le : dimanche 4 avril 2010 - 22:01:03



  • HAL Id : inria-00074685, version 1


Dominique Lavenier. An integrated 2D systolic array for spelling correction. [Research Report] RR-1987, INRIA. 1993. 〈inria-00074685〉



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