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An integrated 2D systolic array for spelling correction

Dominique Lavenier 1
1 API - Parallel VLSI Architectures
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : This paper presents a fully integrated spelling co-processor for speeding up the character string comparison process. The chip we present is architectured around a banded 2-D systolic array consisting of 69 processors and is able to process more than 2 million of words per second. The high regularity of the chip has been exploited for investigating a design methodology based on the automated generation of a representative subcircuit : the kernel.
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Contributor : Rapport de Recherche Inria <>
Submitted on : Wednesday, May 24, 2006 - 4:05:22 PM
Last modification on : Friday, February 12, 2021 - 3:33:15 AM
Long-term archiving on: : Sunday, April 4, 2010 - 10:01:03 PM


  • HAL Id : inria-00074685, version 1


Dominique Lavenier. An integrated 2D systolic array for spelling correction. [Research Report] RR-1987, INRIA. 1993. ⟨inria-00074685⟩



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