]. P. Adam89, D. Adam, H. Juvin, P. Essafi, J. L. Fernandez et al., 4LP -Low Level Language for the Line Processor SYMPATI 2, 12 Colloque GRETSI -Juan-Les-Pins, pp.873-876, 1989.

]. M. Anna87, E. Annaratone, T. Arnould, H. T. Gross, M. Kung et al., The Warp Computer: Architecture, Implementation and Performance, IEEE Transactions on Computers, issue.12, pp.361523-1538, 1987.

]. K. Batc80 and . Batcher, Design of a Massively Parallel Processor, IEEE Transactions on Computers, C, vol.29, issue.9, pp.836-840, 1980.

E. [. Blevins, R. A. Davis, J. H. Heaton, and . Reif, BLITZEN: A highly integrated massively parallel machine, Journal of Parallel and Distributed Computing, vol.8, issue.2, pp.150-160, 1990.
DOI : 10.1016/0743-7315(90)90089-8

]. T. Blan90 and . Blank, The MasPar MP-1 Architecture, Proceedings of IEEE Compcon Spring, pp.20-24, 1990.

]. S. Bork88, R. Borkar, G. Cohn, T. Cox, H. T. Gross et al., iWarp : An Integrated Solution to High-Speed Parallel Computing, Proceedings of Supercomputing '88, pp.330-339, 1988.

]. S. Bork90, R. Borkar, G. Cohn, T. Cox, H. T. Gross et al., Supporting Systolic and Memory Communication in iWarp, Proc. 17th Annual Symposium on Computer Architecture, pp.70-81, 1990.

]. F. Char93 and . Charot, Briques de base pour la réalisation d'architectures parallèles spécialisées, Publication interne, vol.721, 1993.

]. D. Chin88, J. Chin, F. Passe, H. Bernard, E. S. Taylor et al., The Princeton Engine: a real-time video system simulator, IEEE Transactions on Consumer Electronics, vol.34, issue.2, pp.285-297, 1988.
DOI : 10.1109/30.2943

]. M. Duff78 and . Duff, Review of the CLIP Image Processing System, Proc. National Computer Conference, pp.1055-1060, 1978.

]. A. Fihr87, P. T. Fisher, T. E. Highman, and . Rockoff, Architecture of a VLSI SIMD Processing Element, Proc. IEEE conference on Computer Design: VLSI in Computers and Processors, pp.324-327, 1987.

]. A. Fihr88, P. T. Fisher, T. E. Highnam, and . Rockoff, Scan Line Array Processors: Work in Progress, Proc. Image Understanding Workshop, pp.625-633, 1988.

]. A. Fish86 and . Fisher, Scan Line Array Processors for Image Computation, Proc. 13th Annual International Symposium on Computer Architecture, pp.338-345, 1986.

]. T. Fomd88, K. N. Fountain, M. J. Matthews, and . Duff, The CLIP7A Image Processor, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol.10, issue.3, pp.310-319, 1988.

]. H. Head88, K. Heada, H. Kato, K. Matsushima, E. M. Kaneko et al., A Multiprocessor System Utilizing Enhanced DSP's For Image Processing

]. W. Hill85 and . Hillis, The Connection Machine, 1985.

]. D. Hobl91, J. L. Houzet, and J. Y. Basille, ´ evaluation du multiprocesseur SIMD/MIMD GFLOPS sur des algorithmes de traitement d'image, treizì eme Colloque GRETSI -Juan-Les-Pins, pp.1197-1200, 1991.

D. Juvin, J. L. Basille, H. Essafi, and J. Y. , Sympati2, a 1.5d processor array for image applications, EUSIPCO Signal Processing IV : theories and application, pp.311-314, 1988.

]. E. Kesl85, M. O. Kent, E. R. Shneier, and . Lumia, PIPE (Pipelined Image Processing Engine), Journal of Parallel and Distributed Computing, vol.2, pp.50-78, 1985.

]. S. Kung88 and . Kung, VLSI Array processors, IEEE ASSP Magazine, vol.2, issue.3, 1988.
DOI : 10.1109/MASSP.1985.1163741

]. H. Kuwe86, J. A. Kung, and . Webb, Mapping Image Processing Operations onto a Systolic Machine, Journal of Parallel and Distributed Computing, vol.1, issue.4, pp.246-257, 1986.

]. H. Lima89, M. Li, and . Maresca, Polymorphic-Torus Architecture for Computer Vision, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol.11, issue.3, pp.320-330, 1989.

]. R. Lomc80, D. L. Loughead, and . Mccubbrey, The Cytocomputer: A Practical Pipeline Image Processor, Proc. 7th Annual International Symposium on Computer Architecture, pp.271-277, 1980.

]. M. Mali89, H. Maresca, and . Li, Connection Autonomy in SIMD Computers: A VLSI Implementation, Journal of Parallel and Distributed Computing, vol.7, issue.2, pp.302-320, 1989.

]. M. Mall88, M. A. Maresca, E. H. Lavin, and . Li, Parallel Architectures for Vision, Proceedings of the IEEE, vol.76, issue.8, pp.970-981, 1988.

]. A. Mend91, Y. Mérigot, E. F. Ni, and . Devos, Architectures massivementparalì eles pour la vision artificielle, Annales des Télécommunications, vol.46, issue.1 2, pp.78-89, 1991.

]. J. Nick90 and . Nickolls, The Design of the MasPar MP-1: A Cost Effective Massively Parallel COmputer, Proceedings of IEEE Compcon Spring, pp.25-28, 1990.

]. D. Olre85, S. F. Oldfield, and . Reddaway, An Image Understanding performance study on the ICL distributed array processor, Proc. IEEE Workshop on Computer Architecture for Pattern Analysis and Image Database, pp.256-264, 1985.

]. C. Pete90 and . Peterson, 100 MOP LIW Microprocessor for Multicomputers, HOT Chips Symposium II, 1990.

]. L. Scwi88, S. Schmitt, and . Wilson, The AIS-5000 Parallel Processor, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol.10, issue.3, pp.320-330, 1988.

]. H. Sieg81, L. J. Siegel, F. C. Siegel, P. T. Kemmerer, H. Mueller et al., PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition, IEEE Transactions on Computers, issue.12, pp.30934-947, 1981.

]. I. Tahn89, H. Tamitani, E. T. Harasaki, and . Nishitani, A Real-Time HDTV Signal Processor -Architecture and Implementation, Third International Workshop on HDTV, 1989.

]. I. Tami89, H. Tamitani, T. Harasaki, Y. Nishitani, M. Endo et al., A Real-Time Video Signal Processor Suitable for Motion Picture Coding Applications, IEEE Transactions on Circuits and Systems, vol.36, issue.10, pp.1259-1266, 1989.

]. L. Turo88, G. G. Tucker, and . Robertson, Architecture and Applications of the Connection Machine, IEEE Computer, vol.21, issue.8, pp.26-38, 1988.

]. L. Uhr87 and . Uhr, Parallel Computer Vision, 1987.

]. G. Vemd86, S. Verghese, C. R. Mehta, and . Dyer, Image Processing Algorithms for the Pipelined Image-Processing Engine, Research Report, 1986.

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