Interleaved parallel schemes : improving memory throughput on supercomputers

André Seznec 1 Jacques Lenfant 1
1 CALCPAR - Calculateurs Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : On many commercial supercomputers, several vector register processors share a global highly interleaved memory in a MIMD mode. When all the processors are working on a single verctor loop, a significant part of the potential memory throughput may be wasted due to the asynchronism of the processors. In order to limit loss of memory throughput, a SIMD synchronization mode for vector accesses to memory may be used. But an important part of the memory bandwith may be wasted when accessing vectors with an even stride. In this paper, we present IPS, an interleaved parallel scheme, which ensures an equitable distribution of elements on a highly interleaved memory for a wide range a vector strides. We show how to organize access to memory, such that unscrambling of vectors from memory to the vector register processors requires a minimum number of passes through the interconnection network.
Type de document :
[Research Report] RR-1656, INRIA. 1992
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Soumis le : mercredi 24 mai 2006 - 16:50:10
Dernière modification le : jeudi 11 janvier 2018 - 06:21:20
Document(s) archivé(s) le : mardi 12 avril 2011 - 20:00:07



  • HAL Id : inria-00074901, version 1



André Seznec, Jacques Lenfant. Interleaved parallel schemes : improving memory throughput on supercomputers. [Research Report] RR-1656, INRIA. 1992. 〈inria-00074901〉



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