A fault tolerant tightly coupled multiprocessor architecture based on stable transactional memory

Michel Banâtre 1 Philippe Joubert 1
1 LSP - Langages et Systèmes Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires
Abstract : Traditionally, tightly coupled multiprocessors allow data sharing between multiple caches by keeping cached copies of memory blocks coherent with respect to shared memory. This is difficult to achieve in a fault tolerant environment due to the need to save global checkpoints in shared memory from where consistent cache states can be recovered after a failure. The architecture presented in this report solves this problem by encapsulating the memory modifications done by a process into an atomic transaction. Caches record dependencies between the transactions associated with processes modifying the same memory blocks. Dependent transactions may then be atomically committed. Such an operation requires a cache coherence protocol responsible for recording process dependencies as well as keeping coherent cached copies of blocks and a shared stable transactional memory owing to which all memory updates are atomic to allow recovery after a processor failure. This report also presents potential performance for this architecture the data for which was obtained through simulation.
Type de document :
[Research Report] RR-1178, INRIA. 1990
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Contributeur : Rapport de Recherche Inria <>
Soumis le : mercredi 24 mai 2006 - 18:06:11
Dernière modification le : jeudi 11 janvier 2018 - 06:21:20
Document(s) archivé(s) le : mardi 12 avril 2011 - 22:50:17



  • HAL Id : inria-00075380, version 1



Michel Banâtre, Philippe Joubert. A fault tolerant tightly coupled multiprocessor architecture based on stable transactional memory. [Research Report] RR-1178, INRIA. 1990. 〈inria-00075380〉



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