HAL will be down for maintenance from Friday, June 10 at 4pm through Monday, June 13 at 9am. More information
Skip to Main content Skip to Navigation
Reports

Microcoding an abstract machine for parallel logic programming

Abstract : This paper shows the advantages of implementing an abstract intermediate machine for a parallel logical language, on the lower hardware level the FIRMWARE level - of a physical machine which implements basic hardware mechanisms for fast symbolic computation. µSyC, which is a µprogrammable Symbolic Coprocessor under development at the Bull Research Center, has been chosen as a target architecture and the abstract machine in question is the Sequential Parlog Machine which is based on the AND/OR tree execution model for concurrent logical languages such as PARLOG, CP and GHC. The paper describes the µSyC architecture, the language PARLOG, the AND/OR tree model, and the mapping of this model on µSyC. Finally, results for a series of classical benchmark tests is given and compared to other available implementations.
Document type :
Reports
Complete list of metadata

https://hal.inria.fr/inria-00075409
Contributor : Rapport de Recherche Inria Connect in order to contact the contributor
Submitted on : Wednesday, May 24, 2006 - 6:09:43 PM
Last modification on : Friday, February 4, 2022 - 3:18:44 AM
Long-term archiving on: : Tuesday, April 12, 2011 - 11:00:08 PM

Identifiers

  • HAL Id : inria-00075409, version 1

Collections

Citation

A. Rizk, J. Garcia. Microcoding an abstract machine for parallel logic programming. RR-1150, INRIA. 1989. ⟨inria-00075409⟩

Share

Metrics

Record views

45

Files downloads

23