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Microcoding an abstract machine for parallel logic programming

Abstract : This paper shows the advantages of implementing an abstract intermediate machine for a parallel logical language, on the lower hardware level the FIRMWARE level - of a physical machine which implements basic hardware mechanisms for fast symbolic computation. µSyC, which is a µprogrammable Symbolic Coprocessor under development at the Bull Research Center, has been chosen as a target architecture and the abstract machine in question is the Sequential Parlog Machine which is based on the AND/OR tree execution model for concurrent logical languages such as PARLOG, CP and GHC. The paper describes the µSyC architecture, the language PARLOG, the AND/OR tree model, and the mapping of this model on µSyC. Finally, results for a series of classical benchmark tests is given and compared to other available implementations.
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https://hal.inria.fr/inria-00075409
Contributor : Rapport de Recherche Inria <>
Submitted on : Wednesday, May 24, 2006 - 6:09:43 PM
Last modification on : Thursday, February 11, 2021 - 2:50:07 PM
Long-term archiving on: : Tuesday, April 12, 2011 - 11:00:08 PM

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  • HAL Id : inria-00075409, version 1

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A. Rizk, J. Garcia. Microcoding an abstract machine for parallel logic programming. RR-1150, INRIA. 1989. ⟨inria-00075409⟩

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