FPGA Implementation of a Recently Published Signature Scheme

Jean-Luc Beuchat 1 Nicolas Sendrier 1 Arnaud Tisserand 1 Gilles Villard 1
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical.
Type de document :
[Research Report] RR-5158, INRIA. 2004
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Contributeur : Rapport de Recherche Inria <>
Soumis le : lundi 29 mai 2006 - 11:58:57
Dernière modification le : samedi 21 avril 2018 - 01:27:22
Document(s) archivé(s) le : lundi 5 avril 2010 - 21:34:37



  • HAL Id : inria-00077045, version 1



Jean-Luc Beuchat, Nicolas Sendrier, Arnaud Tisserand, Gilles Villard. FPGA Implementation of a Recently Published Signature Scheme. [Research Report] RR-5158, INRIA. 2004. 〈inria-00077045〉



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