About cache associativity in low-cost shared memory multi-microprocessors

Nathalie Drach 1 Alain Gefflaut 2 Philippe Joubert 2 André Seznec 1
1 CALCPAR - Calculateurs Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
2 LSP - Langages et Systèmes Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires
Abstract : In 1993, sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly usedin the design of a low cost single-bus shared memory multiprocessors with-out using any second-level cache. In this paper, we explore theviability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently proposed innovative cache structures, the skewed associative cache organization and the semi-unified cache organization are shown to work fine.
Type de document :
Rapport
[Research Report] RR-2083, INRIA. 1993
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https://hal.inria.fr/inria-00077193
Contributeur : Rapport de Recherche Inria <>
Soumis le : lundi 29 mai 2006 - 17:17:05
Dernière modification le : mercredi 11 avril 2018 - 02:01:30
Document(s) archivé(s) le : lundi 5 avril 2010 - 21:42:07

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Nathalie Drach, Alain Gefflaut, Philippe Joubert, André Seznec. About cache associativity in low-cost shared memory multi-microprocessors. [Research Report] RR-2083, INRIA. 1993. 〈inria-00077193〉

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