Evolvable platform for array processing: a one-chip approach

Abstract : The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array (FPPA). The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10x10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz for processors (20 MHz for communications). The very low power feature of the core processor results in a 1 Watt power consumption for the whole array at 5 MHz and makes it particularly interesting for portable devices that require quite complex algorithms. In addition, FPPA principe, i.e., fault-tolerant large array of cells interconnected with an asynchronous communication scheme, is applicable on alternative structures for the cell architecture.
Type de document :
Communication dans un congrès
MicroNeuro, Apr 1999, Granada, Spain, France. 1999
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https://hal.inria.fr/inria-00098897
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Soumis le : mardi 26 septembre 2006 - 08:40:04
Dernière modification le : jeudi 11 janvier 2018 - 06:19:48

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  • HAL Id : inria-00098897, version 1

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Bernard Girau, Pierre Marchal, Pascal Nussbaum, Arnaud Tisserand, Hector Fabio Restrepo. Evolvable platform for array processing: a one-chip approach. MicroNeuro, Apr 1999, Granada, Spain, France. 1999. 〈inria-00098897〉

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