HAL will be down for maintenance from Friday, June 10 at 4pm through Monday, June 13 at 9am. More information
Skip to Main content Skip to Navigation
Conference papers

Evolvable platform for array processing: a one-chip approach

Abstract : The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array (FPPA). The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10x10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz for processors (20 MHz for communications). The very low power feature of the core processor results in a 1 Watt power consumption for the whole array at 5 MHz and makes it particularly interesting for portable devices that require quite complex algorithms. In addition, FPPA principe, i.e., fault-tolerant large array of cells interconnected with an asynchronous communication scheme, is applicable on alternative structures for the cell architecture.
Document type :
Conference papers
Complete list of metadata

Contributor : Publications Loria Connect in order to contact the contributor
Submitted on : Tuesday, September 26, 2006 - 8:40:04 AM
Last modification on : Friday, February 4, 2022 - 3:22:04 AM


  • HAL Id : inria-00098897, version 1



Bernard Girau, Pierre Marchal, Pascal Nussbaum, Arnaud Tisserand, Hector Fabio Restrepo. Evolvable platform for array processing: a one-chip approach. MicroNeuro, Apr 1999, Granada, Spain, France. ⟨inria-00098897⟩



Record views