Neural computation paradigms may be defined to counterbalance the topological problems of digital hardware implementations of neural networks. The use of such paradigms naturally leads to neural models that are more tolerant of hardware constraints. A theoretical and practical framework called FPNA aims at developing such neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. These Field Programmable Neural Arrays reconcile the high connection density of neural architectures with the need of a limited interconnection scheme in hardware implementations. This paper focuses on the FPNA-based simplification of the architecture of a multilayer shortcut perceptron used in a pattern classification problem.