# A Very High Density VLSI Implementation of Threshold Network Ensembles (TNE)

1 CORTEX - Neuromimetic intelligence
INRIA Lorraine, LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications
Abstract : This paper describes a hardware implementation of threshold network ensembles (TNE) for classification applications. We first describe the algorithm and compare its performance with those of individual classifiers such as binary neural network and support vector machine (SVM). The effect of limited precision on the performance of threshold network ensembles is also investigated. The proposed multi-precision architecture is then mapped into a scalable systolic architecture implemented first on a single VLSI chip. The modularity and the easy programmability of the basic chip has made possible the extension of the architecture to a low cost multi-chip solution. We propose a 3D packaged circuit in which 12 basic chips have been integrated into a very compact volume of $(2 \times 2 \times 0.7) cm^3$. Successful operation of the 3D prototype is demonstrated through experimental test results of the chip.
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Type de document :
Communication dans un congrès
IEEE International Conference on Acoustics, Speech, and Signal Processing - ICASSP'2003, Apr 2003, Hong Kong, Chine, 2003
Domaine :

https://hal.inria.fr/inria-00099643
Contributeur : Publications Loria <>
Soumis le : mardi 26 septembre 2006 - 09:39:44
Dernière modification le : jeudi 11 janvier 2018 - 06:19:48

### Identifiants

• HAL Id : inria-00099643, version 1

### Citation

Amine Bermak, Dominique Martinez. A Very High Density VLSI Implementation of Threshold Network Ensembles (TNE). IEEE International Conference on Acoustics, Speech, and Signal Processing - ICASSP'2003, Apr 2003, Hong Kong, Chine, 2003. 〈inria-00099643〉

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