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Hardware-friendly neural computation of symmetric boolean functions

Bernard Girau 1
1 CORTEX - Neuromimetic intelligence
INRIA Lorraine, LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications
Abstract : The theoretical and practical framework of Field Programmable Neural Arrays has been defined to reconcile simple hardware topologies with complex neural architectures: FPNAs lead to powerful neural models whose original data exchange scheme allows to use hardware-friendly neural topologies. This report addresses preliminary results in the study of the computation power of FPNAs. The computation of symmetric boolean functions (e.g. the n-dimensional parity problem) is taken as a textbook example. The FPNA concept allows successive topology simplifications of standard neural models for such functions, so that the number of weights is reduced with a factor up to n with respect to previous works.
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Contributor : Publications Loria <>
Submitted on : Thursday, October 19, 2006 - 9:12:11 AM
Last modification on : Friday, February 26, 2021 - 3:28:03 PM
Long-term archiving on: : Friday, November 25, 2016 - 12:49:57 PM


  • HAL Id : inria-00107867, version 1



Bernard Girau. Hardware-friendly neural computation of symmetric boolean functions. [Intern report] A00-R-024 || girau00n, 2000, 8 p. ⟨inria-00107867⟩



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