MLP computing and learning on FPGA using on-line arithmetic

Bernard Girau 1 Arnaud Tisserand
1 CORTEX - Neuromimetic intelligence
INRIA Lorraine, LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications
Abstract : The use of reprogrammable hardware devices may lead to efficient, flexible and cheap neural network hardware implementations. Yet the area and connectivity constraints of FPGAs limit their use to rather small and already learned neural networks. A general method to implement both computing and learning of multilayer perceptrons of any size on FPGAs is described. A serial arithmetic, called on-line arithmetic, is used in order to improve parallelism despite the area constraints of the FPGA. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation. Our method is applied to the standard NetTalk benchmark, in order to show how large neural networks may be efficiently implemented on a single FPGA and a single memory chip.
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Article dans une revue
Int. Journal on System Research and Information Science, 1999, 21 p
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https://hal.inria.fr/inria-00108064
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Soumis le : jeudi 19 octobre 2006 - 15:40:37
Dernière modification le : jeudi 11 janvier 2018 - 06:19:48

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  • HAL Id : inria-00108064, version 1

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Bernard Girau, Arnaud Tisserand. MLP computing and learning on FPGA using on-line arithmetic. Int. Journal on System Research and Information Science, 1999, 21 p. 〈inria-00108064〉

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