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Scheduling issues on thermally-constrained processors

Pierre Michaud 1 Yiannakis Sazeides 2
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : The relentless increase of power density has rendered temperature a primary design constraint for microprocessors. Although a power density increase does not necessarily lead to a higher time-average temperature, we show in this study that it increases the amplitude of temperature oscillations. As a consequence, thermal throttling may be engaged more often and degrade performance. We establish that a possible way to decrease the amplitude of temperature oscillations is to increase their frequency. In a multiprogrammed environment, executing multiple threads/processes alternately can result in temperature oscillations if different threads generate different power densities. We therefore suggest that, as power density increases and processors get faster, the time slice can and should be decreased. Using a short time slice also enables the operating system to take advantage of activity migration without special architectural support. Indeed, on a thermally constrained multi-core (TCMC), activity migration can be leveraged to decrease temperature by better distributing heat over the different cores. Furthermore, we show that fair scheduling with different thread priorities can be achieved but requires sometimes to run simultaneously fewer threads than cores when fewer threads are sufficient to maintain the TCMC at thermal saturation. We propose a scheduling method that implements activity migration while taking into consideration different thread priorities. We show that, under a temperature constraint, this scheduling method provides a fair partitioning of the overall computing power of a TCMC while delivering a global execution throughput close to the maximum throughput.
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https://hal.inria.fr/inria-00110507
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Submitted on : Monday, October 30, 2006 - 1:55:08 PM
Last modification on : Thursday, January 7, 2021 - 4:36:18 PM
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  • HAL Id : inria-00110507, version 1

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Pierre Michaud, Yiannakis Sazeides. Scheduling issues on thermally-constrained processors. [Research Report] PI 1822, 2006, pp.19. ⟨inria-00110507⟩

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