Parallel Image Quilting-A Case Study on Partitioning and Scheduling on CMP

Jean-Claude Paul 1 Songliu Guo 1 Weiming Dong 1 Dongsheng Wang 1
1 CAD - Computer Aided Design
LIAMA - Laboratoire Franco-Chinois d'Informatique, d'Automatique et de Mathématiques Appliquées, Inria Paris-Rocquencourt
Abstract : Chip-multiprocessor is one of the most popular architectures for the coming SOC times. It makes good use of the huge amount of transistors and is also very easy for software design. In this paper, we proposed a map of parallel image quilting on CMP, which is a widely used algorithm for texture synthesis in Computer Graphics and Computer Vision. Our algorithm obtained nearly linear speeding up performance, as well as nice power e±ciency and good scalability.
Type de document :
Communication dans un congrès
Workshop on State-of-the-Art in Scientific and Parallel Computing (PARA' 06)., Jun 2006, Umeå / Sweden, 2006
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https://hal.inria.fr/inria-00139876
Contributeur : Chine Publications Liama <>
Soumis le : mardi 3 avril 2007 - 16:59:20
Dernière modification le : jeudi 11 janvier 2018 - 01:46:20

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  • HAL Id : inria-00139876, version 1

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Jean-Claude Paul, Songliu Guo, Weiming Dong, Dongsheng Wang. Parallel Image Quilting-A Case Study on Partitioning and Scheduling on CMP. Workshop on State-of-the-Art in Scientific and Parallel Computing (PARA' 06)., Jun 2006, Umeå / Sweden, 2006. 〈inria-00139876〉

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