An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63 ,
DOI : 10.1109/ASYNC.2005.10
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06), pp.172-181, 2006. ,
DOI : 10.1109/ASYNC.2006.16
Introduction to the ISO specification language LOTOS, Computer Networks and ISDN Systems, vol.14, issue.1, pp.25-59, 1988. ,
DOI : 10.1016/0169-7552(87)90085-7
Efficient on-the-fly model-checking for regular alternation-free mu-calculus, Science of Computer Programming, vol.46, issue.3, pp.255-281, 2003. ,
DOI : 10.1016/S0167-6423(02)00094-1
URL : https://hal.archives-ouvertes.fr/inria-00072755
Validation of Asynchronous Circuit Specifications Using IF/CADP, Proc. of VLSI-SoC 2003, pp.86-91 ,
DOI : 10.1007/0-387-33403-3_6
URL : https://hal.archives-ouvertes.fr/hal-00107431
The odd-even turn model for adaptive routing, IEEE Transactions on Parallel and Distributed Systems, vol.11, issue.7, pp.729-738, 2000. ,
DOI : 10.1109/71.877831
The verification of asynchronous circuits using CCS, 1997. ,
FAUST : On-chip distributed architecture for a 4G baseband modem SoC, Proc. of Design and Reuse IP-SOC 2005, pp.51-55 ,
Balsa: An Asynchronous Hardware Synthesis Language, The Computer Journal, vol.45, issue.1, pp.12-18, 2002. ,
DOI : 10.1093/comjnl/45.1.12
URL : http://comjnl.oxfordjournals.org/cgi/content/short/45/1/12
SVL: A Scripting Language for Compositional Verification, Proc. of FORTE, pp.377-392, 2001. ,
DOI : 10.1007/0-306-47003-9_24
URL : https://hal.archives-ouvertes.fr/inria-00072396
Compiler Construction Using LOTOS NT, Proc. of CC, pp.9-13, 2002. ,
DOI : 10.1007/3-540-45937-5_3
An overview of CADP, EASST Newsletter, vol.4, pp.13-24, 2001. ,
URL : https://hal.archives-ouvertes.fr/inria-00069920
Verifying and Testing Asynchronous Circuits Using Lotos, Proc. of FORTE/PSTV, pp.267-283, 2000. ,
DOI : 10.1007/978-0-387-35533-7_17
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.30.553
Communicating Sequential Processes, 1985. ,
LOTOS ? a formal description technique based on the temporal ordering of observational behaviour, International Organization for Standardization ? Information Processing Systems ? Open Systems Interconnection, 1989. ,
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench, Information Processing Letters, vol.89, issue.6, pp.293-296, 2004. ,
DOI : 10.1016/j.ipl.2003.12.007
Verification and implementation of delay-insensitive processes in restrictive environments, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004., pp.21-48, 2006. ,
DOI : 10.1109/CSD.2004.1309119
The tangram framework (embedded tutorial), Proceedings of the 2001 conference on Asia South Pacific design automation , ASP-DAC '01, pp.255-260 ,
DOI : 10.1145/370155.370339
Pipelined asynchronous circuits. Master's thesis , California Institute of Technology, 1995. ,
Slack elasticity in concurrent computing, Proc. of MPC, pp.272-285, 1998. ,
DOI : 10.1007/BFb0054295
The probe: An addition to communication primitives, Information Processing Letters, vol.20, issue.3, pp.125-130, 1985. ,
DOI : 10.1016/0020-0190(85)90078-X
Compiling communicating processes into delay-insensitive VLSI circuits, Distributed Computing, pp.226-234, 1986. ,
DOI : 10.1007/BF01660034
URL : http://authors.library.caltech.edu/26661/2/postscript.pdf
Communication and Concurrency, 1989. ,
Practicality of state-machine verification of speed-independent circuits, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, pp.266-269, 1989. ,
DOI : 10.1109/ICCAD.1989.76950
Haste Manual, Version 3.0. Handshake Solutions [27] B. Rahardjo. SPIN as a hardware design tool, Proc. of SPIN, 1995. ,
Translating Hardware Process Algebras into Standard Process Algebras: Illustration with CHP and LOTOS, Proc. of IFM 2005, pp.287-306 ,
DOI : 10.1007/11589976_17
A formal model for defining and classifying delay-insensitive circuits and systems, Distributed Computing, vol.30, issue.2, pp.197-204, 1986. ,
DOI : 10.1007/BF01660032
On process-algebraic verification of asynchronous circuits, Sixth International Conference on Application of Concurrency to System Design (ACSD'06), pp.37-46, 2006. ,
DOI : 10.1109/ACSD.2006.16
LOTOS/CADP-based verification of asynchronous circuits, 2001. ,