A. Colin and I. Puaut, A modular and retargetable framework for tree-based WCET analysis, Proceedings 13th Euromicro Conference on Real-Time Systems, pp.37-44, 2001.
DOI : 10.1109/EMRTS.2001.933995

P. Cousot and R. Cousot, Abstract interpretation, Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages , POPL '77, pp.238-252, 1977.
DOI : 10.1145/512950.512973
URL : https://hal.archives-ouvertes.fr/inria-00528590

P. Cousot and R. Cousot, Basic Concepts of Abstract Interpretation, pp.359-366, 2004.
DOI : 10.1007/978-1-4020-8157-6_27

C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt et al., Reliable and Precise WCET Determination for a Real-Life Processor, EMSOFT '01: Proceedings of the First International Workshop on Embedded Software, pp.469-485, 2001.
DOI : 10.1007/3-540-45449-7_32

S. Ghosh, M. Martonosi, and S. Malik, Cache miss equations: a compiler framework for analyzing and tuning memory behavior, ACM Transactions on Programming Languages and Systems, vol.21, issue.4, pp.703-746, 1999.
DOI : 10.1145/325478.325479

R. Heckmann, M. Langenbach, S. Thesing, and R. Wilhelm, The influence of processor architecture on the design and the results of WCET tools, Proceedings of the IEEE, p.7, 2003.
DOI : 10.1109/JPROC.2003.814618

X. Li, A. Roychoudhury, and T. Mitra, Modeling out-of-order processors for wcet estimation . Real-Time Systems Journal, 2006.

T. Lundqvist and P. Stenström, Timing anomalies in dynamically scheduled microprocessors, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054), pp.12-21, 1999.
DOI : 10.1109/REAL.1999.818824

F. Mueller, Static cache simulation and its applications, 1994.

F. Mueller, Timing predictions for multi-level caches, ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pp.29-36, 1997.

F. Mueller, Timing analysis for instruction caches. Real-Time Syst, pp.217-247, 2000.

H. S. Negi, T. Mitra, and A. Roychoudhury, Accurate estimation of cache-related preemption delay, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis , CODES+ISSS '03, pp.201-206, 2003.
DOI : 10.1145/944645.944698

I. Puaut, WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems, 18th Euromicro Conference on Real-Time Systems (ECRTS'06)
DOI : 10.1109/ECRTS.2006.32

P. Puschner and C. Koza, Calculating the maximum execution time of real-time programs. Real-Time Syst, pp.159-176, 1989.

P. Puschner and A. V. Schedl, Computing maximum task execution times ? a graph based approach, Proceedings of IEEE Real-Time Systems Symposium, pp.67-91, 1997.

H. Ramaprasad and F. Mueller, Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns, 11th IEEE Real Time and Embedded Technology and Applications Symposium, pp.148-157, 2005.
DOI : 10.1109/RTAS.2005.12

J. Staschulat, S. Schliecker, and R. Ernst, Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay, 17th Euromicro Conference on Real-Time Systems (ECRTS'05), pp.41-48, 2005.
DOI : 10.1109/ECRTS.2005.26

H. Theiling, C. Ferdinand, and R. Wilhelm, Fast and precise WCET prediction by separated cache and path analyses. Real-Time Syst, pp.157-179, 2000.

X. Vera, B. Lisper, and J. Xue, Data caches in multitasking hard real-time systems, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748), 2003.
DOI : 10.1109/REAL.2003.1253263

R. White, F. Mueller, C. Healy, D. Whalley, and M. Harmon, Timing analysis for data caches and set-associative caches, Proceedings Third IEEE Real-Time Technology and Applications Symposium, pp.192-202, 1997.
DOI : 10.1109/RTTAS.1997.601358