Abstract: Large System-on-Chips are built by assembly of existing components modeled at different representation levels (TLM, RTL). The IP-Xact standard was developed to ease interoperability of IPs from different vendors. Currently, it focuses on structural, typing and memory-related information and does not fully face behavioral and timing representation issues. UML Marte profile explicitly focuses on the rich expression of time (physical or logical). Combining both specifications allows for introducing a higher timed representation level and for extending IP-Xact with timing characteristics. Such timing characteristics are used to validate IP-Xact models by composing component behaviors and compare existing TLM and RTL implementations.