A unified runtime system for heterogeneous multicore architectures

Cédric Augonnet 1, 2 Raymond Namyst 1, 2
2 RUNTIME - Efficient runtime systems for parallel architectures
Inria Bordeaux - Sud-Ouest, CNRS - Centre National de la Recherche Scientifique : UMR5800, UB - Université de Bordeaux
Abstract : Approaching the theoretical performance of heterogeneous multicore architectures, equipped with specialized accelerators, is a challenging issue. Unlike regular CPUs that can transparently access the whole global memory address range, accelerators usually embed local memory on which they perform all their computations using a specific instruction set. While many research efforts have been devoted to offloading parts of a program over such coprocessors, the real challenge is to find a programming model providing a unified view of all available computing units. In this paper, we present an original runtime system providing a high-level, unified execution model allowing seamless execution of tasks over the underlying heterogeneous hardware. The runtime is based on a hierarchical memory management facility and on a codelet scheduler. We demonstrate the efficiency of our solution with a LU decomposition for both homogeneous (3.8 speedup on 4 cores) and heterogeneous machines (95% efficiency). We also show that a "granularity aware" scheduling can improve execution time by 35%.
Type de document :
Communication dans un congrès
2nd Workshop on Highly Parallel Processing on a Chip (HPPC 2008), Aug 2008, Las Palmas de Gran Canaria, Spain. 2008


https://hal.inria.fr/inria-00326917
Contributeur : Cédric Augonnet <>
Soumis le : lundi 6 octobre 2008 - 14:51:18
Dernière modification le : jeudi 10 septembre 2015 - 01:06:24
Document(s) archivé(s) le : lundi 8 octobre 2012 - 14:01:55

Fichier

AugNam08HPPC.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

  • HAL Id : inria-00326917, version 1

Collections

Citation

Cédric Augonnet, Raymond Namyst. A unified runtime system for heterogeneous multicore architectures. 2nd Workshop on Highly Parallel Processing on a Chip (HPPC 2008), Aug 2008, Las Palmas de Gran Canaria, Spain. 2008. <inria-00326917>

Partager

Métriques

Consultations de
la notice

397

Téléchargements du document

297