Skip to Main content Skip to Navigation
New interface
Conference papers

A unified runtime system for heterogeneous multicore architectures

Cédric Augonnet 1, 2 Raymond Namyst 1, 2 
2 RUNTIME - Efficient runtime systems for parallel architectures
Inria Bordeaux - Sud-Ouest, UB - Université de Bordeaux, CNRS - Centre National de la Recherche Scientifique : UMR5800
Abstract : Approaching the theoretical performance of heterogeneous multicore architectures, equipped with specialized accelerators, is a challenging issue. Unlike regular CPUs that can transparently access the whole global memory address range, accelerators usually embed local memory on which they perform all their computations using a specific instruction set. While many research efforts have been devoted to offloading parts of a program over such coprocessors, the real challenge is to find a programming model providing a unified view of all available computing units. In this paper, we present an original runtime system providing a high-level, unified execution model allowing seamless execution of tasks over the underlying heterogeneous hardware. The runtime is based on a hierarchical memory management facility and on a codelet scheduler. We demonstrate the efficiency of our solution with a LU decomposition for both homogeneous (3.8 speedup on 4 cores) and heterogeneous machines (95% efficiency). We also show that a "granularity aware" scheduling can improve execution time by 35%.
Document type :
Conference papers
Complete list of metadata

Cited literature [16 references]  Display  Hide  Download
Contributor : Cédric Augonnet Connect in order to contact the contributor
Submitted on : Monday, October 6, 2008 - 2:51:18 PM
Last modification on : Saturday, June 25, 2022 - 7:47:27 PM
Long-term archiving on: : Monday, October 8, 2012 - 2:01:55 PM


Files produced by the author(s)


  • HAL Id : inria-00326917, version 1



Cédric Augonnet, Raymond Namyst. A unified runtime system for heterogeneous multicore architectures. 2nd Workshop on Highly Parallel Processing on a Chip (HPPC 2008), Aug 2008, Las Palmas de Gran Canaria, Spain. ⟨inria-00326917⟩



Record views


Files downloads