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Accurate analysis of memory latencies for WCET estimation

Abstract : These last years, many researchers have proposed solutions to estimate the Worst-Case Execution Time of a critical application when it is run on modern hardware. Several schemes commonly implemented to improve performance have been considered so far in the context of static WCET analysis: pipelines, instruction caches, dynamic branch predictors, execution cores supporting out-of-order execution, etc. Comparatively, components that are external to the processor have received lesser attention. In particular, the latency of memory accesses is generally considered as a fixed value. Now, modern DRAM devices support the open page policy that reduces the memory latency when successive memory accesses address the same memory row. This scheme, also known as row buffer, induces variable memory latencies, depending on whether the access hits or misses in the row buffer. In this paper, we propose an algorithm to take the open page policy into account when estimating WCETs for a processor with an instruction cache. Experimental results show that WCET estimates are refined thanks to the consideration of tighter memory latencies instead of pessimistic values.
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https://hal.inria.fr/inria-00336530
Contributor : Anne Jaigu <>
Submitted on : Tuesday, November 4, 2008 - 1:43:20 PM
Last modification on : Wednesday, September 15, 2021 - 10:39:37 AM
Long-term archiving on: : Monday, June 7, 2010 - 10:44:47 PM

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  • HAL Id : inria-00336530, version 1

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Roman Bourgade, Clément Ballabriga, Hugues Cassé, Christine Rochange, Pascal Sainrat. Accurate analysis of memory latencies for WCET estimation. 16th International Conference on Real-Time and Network Systems (RTNS 2008), Isabelle Puaut, Oct 2008, Rennes, France. ⟨inria-00336530⟩

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