On-Line Arithmetic Based Reprogrammable Hardware Implementation of LVQ Neural Network for Alertness Classification

Abstract : The current study presents the hardware implementation of a learning Vector Quantization (LVQ) neural network. Starting from the spectral EEG analysis, we suggest an LVQ serial on-line architecture implementation on a Field programmable Gate Array (FPGA) circuit. Our concern was mainly to get a light, easy-to-wear system for the classification of vigilance levels in humans using EEG signals. The results of these classified states by LVQ mode are presented in this paper. Furthermore, the highly satisfactory performances of our implementation in terms of area speed and delay are described.
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Article dans une revue
IJCSNS International Journal of Computer Science and Network Security, Dr. Sang H. Lee, 2008, 8 (3), pp.260-266
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https://hal.inria.fr/inria-00338767
Contributeur : Bernard Girau <>
Soumis le : vendredi 14 novembre 2008 - 11:53:41
Dernière modification le : jeudi 1 février 2018 - 16:34:02

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  • HAL Id : inria-00338767, version 1

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M. Boubaker, Khaled Ben Khalifa, Bernard Girau, Mohamed Dogui, Mohamed Hédi Bedoui. On-Line Arithmetic Based Reprogrammable Hardware Implementation of LVQ Neural Network for Alertness Classification. IJCSNS International Journal of Computer Science and Network Security, Dr. Sang H. Lee, 2008, 8 (3), pp.260-266. 〈inria-00338767〉

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