On using an hybrid MPI-Thread programming for the implementation of a parallel sparse direct solver on a network of SMP nodes

Pascal Hénon 1 Pierre Ramet 1, 2 Jean Roman 1, 2
1 SCALAPPLIX - Algorithms and high performance computing for grand challenge applications
Université Bordeaux Segalen - Bordeaux 2, Université Sciences et Technologies - Bordeaux 1, Inria Bordeaux - Sud-Ouest, École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB), CNRS - Centre National de la Recherche Scientifique : UMR5800
Abstract : Since the last decade, most of the supercomputer architectures are based on cluster of SMP nodes. In those architectures the exchanges between processors are made through shared memory when the processor are located on a same SMP node and through the network otherwise. Generally, the MPI implementations provided by the constructor on those machines are adapted to this situation and take advantage of the share memory to treat messages between processors in a same SMP node. Nevertheless, this transparent approach to exploit shared memory do not avoid the storage of buffers needed in asynchronous communications. In the parallel direct solvers the storage of these buffers can become a bottleneck. In this paper, we propose an hybrid thread-MPI implementation of a direct solver and analyse the benefits of this approach in term of memory and run-time performances.
keyword : Sparse
Type de document :
Communication dans un congrès
Sixth International Conference on Parallel Processing and Applied Mathematics, Workshop HPC Linear Algebra, 2005, Poznan, Poland. Springer Verlag, 3911, pp.1050--1057, 2005, LNCS
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Contributeur : Pierre Ramet <>
Soumis le : jeudi 11 décembre 2008 - 19:24:37
Dernière modification le : jeudi 11 janvier 2018 - 06:22:12

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  • HAL Id : inria-00346610, version 1

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Pascal Hénon, Pierre Ramet, Jean Roman. On using an hybrid MPI-Thread programming for the implementation of a parallel sparse direct solver on a network of SMP nodes. Sixth International Conference on Parallel Processing and Applied Mathematics, Workshop HPC Linear Algebra, 2005, Poznan, Poland. Springer Verlag, 3911, pp.1050--1057, 2005, LNCS. 〈inria-00346610〉

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