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Test Coverage for Loose Timing Annotations

Abstract : The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tools. These levels are called transactional, because systems are described as asynchronous parallel activities communicating by transactions. The most abstract transactional model is purely functional. The following model in the design flow is annotated with some timing information on the duration of the main components, that serves for performance evaluation. The timing annotations are included as special wait instructions, but since the timing information is imprecise, it should not result in additional synchronizations. We would like the functional properties of the system to be independent of the precise timing. In previous work [1], we showed how to adapt dynamic partial order reduction techniques to functional models of SoCs written in SystemC, in order to guarantee that functional properties are schedulerindependent. In this paper, we extend this work to timed systems with bounded delays, in order to guarantee timing-independence. The idea is to generate a set of executions that covers small variations of the timing annotations.
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https://hal.inria.fr/inria-00350936
Contributor : Claude Helmstetter <>
Submitted on : Wednesday, January 7, 2009 - 6:19:08 PM
Last modification on : Thursday, November 19, 2020 - 3:58:01 PM
Long-term archiving on: : Tuesday, June 8, 2010 - 4:56:33 PM

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Claude Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz. Test Coverage for Loose Timing Annotations. Formal Methods for Industrial Critical Systems (FMICS), Aug 2006, Bonn, Germany. ⟨inria-00350936⟩

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