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From MARTE to dynamically reconfigurable FPGAs : Introduction of a control extension in a model based design flow

Imran Rafiq Quadri 1 Samy Meftali 1 Jean-Luc Dekeyser 1
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : System-on-Chip (SoC) can be considered as a particular case of embedded systems and has rapidly became a de-facto solution for implement- ing these complex systems. However, due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless method- ologies and tools to handle the SoC co-design aspects. This paper addresses this issue and proposes a novel SoC co-design methodology based on Model Driven Engineering (MDE) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by OMG (Object Management Group), in order to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs; and allow to implement the notion of Partial Dy- namic Reconfiguration supported by current FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in UML (Unified Modeling Language); and afterwards, transform these high level mod- els into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis.
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https://hal.inria.fr/inria-00365061
Contributor : Imran Rafiq Quadri <>
Submitted on : Monday, March 2, 2009 - 11:04:09 AM
Last modification on : Thursday, February 21, 2019 - 10:52:49 AM
Long-term archiving on: : Tuesday, June 8, 2010 - 11:02:53 PM

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  • HAL Id : inria-00365061, version 1

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Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. From MARTE to dynamically reconfigurable FPGAs : Introduction of a control extension in a model based design flow. [Research Report] RR-6862, INRIA. 2009. ⟨inria-00365061⟩

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