CCSL: specifying clock constraints with UML/MARTE

Frédéric Mallet 1
1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : The Object Management Group (OMG) Unified Modeling Manguage (UML) profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) aims at using the general-purpose modeling language UML in the domain of Real-Time and Embedded (RTE) systems. To achieve this goal, it is absolutely required to introduce inside the mainly untimed UML an unambiguous time structure which MARTE model elements can rely on to build precise models amenable to formal analysis. The MARTE Time model has defined such a structure. We have also defined a non-normative concrete syntax called the Clock Constraint Specification Language (CCSL) to demonstrate what can be done based on this structure. This paper gives a brief overview of this syntax and its formal semantics, and shows how existing UML model elements can be used to apply this syntax in a graphical way and benefit from the semantics.
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Innovations in Systems and Software Engineering, Springer Verlag, 2008, Special Issue on UML & Formal Methods, 4 (3), pp.309-314. <10.1007/s11334-008-0055-2>
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https://hal.inria.fr/inria-00371371
Contributeur : Frédéric Mallet <>
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Dernière modification le : vendredi 10 avril 2009 - 16:09:20
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Frédéric Mallet. CCSL: specifying clock constraints with UML/MARTE. Innovations in Systems and Software Engineering, Springer Verlag, 2008, Special Issue on UML & Formal Methods, 4 (3), pp.309-314. <10.1007/s11334-008-0055-2>. <inria-00371371>

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