Energy efficient computing is a major concern in all EDA industry, due mainly to cost, reliability and feasibility: temperature and power are themain performance limiters. Dynamic Variable Stages Pipelines allows to improve processors and data-paths throughput while reducing their energy consumptions. When the clock frequency is lowered, more computations can be performed in a combinatorial way. In such case, signals can go farther away than the fixed pipelines boundaries needed to ensure correct behaviour at high-frequency clock. Dynamic Variables Stages Pipelines allow to save dynamic power when stalling clock on bypassed pipeline buffers. This paper copes with the control for such Dynamic Variable Stages Pipelines. The control must ensure correct mode switches from/to Long Pipeline High Frequency and Short Pipeline Low Frequency. We provide an implementation with distributed control, and another one with centralized control, allowing to cope with very long pipelines where physical latencies can cause feasibility issues.