H. Benton, A. P. Calhoun, and . Chandrakasan, Ultra-dynamic voltage scaling (udvs) using sub-threshold operation and local voltage dithering, IEEE Journal of Solid-State Circuits, vol.41, issue.1, pp.238-245, 2006.

B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin et al., High performance fully-depleted tri-gate CMOS transistors, IEEE Electron Device Letters, vol.24, issue.4, pp.263-265, 2003.
DOI : 10.1109/LED.2003.810888

M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design, 2008.

C. Long and L. He, Distributed sleep transistor network for power reduction, Proceedings of the 40th conference on Design automation , DAC '03, pp.181-186, 2003.
DOI : 10.1145/775832.775879

G. Siva, A. Narendra, and . Chandrakasan, Leakage in Nanometer CMOS Technologies, 2005.

J. Pouwelse, K. Langendoen, and H. Sips, Dynamic voltage scaling on a low-power microprocessor, Proceedings of the 7th annual international conference on Mobile computing and networking , MobiCom '01, pp.251-259, 2001.
DOI : 10.1145/381677.381701

T. Sasaki, Y. Ichikawa, T. Hironaka, T. Kitamura, and T. Kondo, Evaluation of low-energy and high-performance processor using variable stages pipeline technique, Computers and Digital Techniques, IET, pp.230-238, 2008.
DOI : 10.1049/iet-cdt:20070130

H. Shimada, H. Ando, and T. Shimada, Pipeline stage unification, Proceedings of the 2003 international symposium on Low power electronics and design , ISLPED '03, pp.326-329, 2003.
DOI : 10.1145/871506.871587

J. Yao, S. Miwa, H. Shimada, and S. Tomita, Optimal pipeline depth with pipeline stage unification adoption, ACM SIGARCH Computer Architecture News, vol.35, issue.5, pp.3-9, 2007.
DOI : 10.1145/1360464.1360470