Asynchronous design methodologies: an overview, Proceedings of the IEEE, vol.83, issue.1, pp.69-93, 1995. ,
DOI : 10.1109/5.362752
Scanning the technology: Applications of asynchronous circuits, Proceedings of the IEEE, special issue on Asynchronous Circuits and Systems, pp.223-233, 1999. ,
Compiling communicating processes into delay-insensitive VLSI circuits, Distributed Computing, vol.20, issue.8, pp.226-234, 1986. ,
DOI : 10.1007/BF01660034
Balsa: An Asynchronous Hardware Synthesis Language, The Computer Journal, vol.45, issue.1, pp.12-18, 2002. ,
DOI : 10.1093/comjnl/45.1.12
The tangram framework (embedded tutorial), Proceedings of the 2001 conference on Asia South Pacific design automation , ASP-DAC '01, pp.255-260, 2001. ,
DOI : 10.1145/370155.370339
Introduction to Process Algebra, Texts in Theoretical Computer Science, 2000. ,
The probe: An addition to communication primitives, Information Processing Letters, vol.20, issue.3, pp.125-130, 1985. ,
DOI : 10.1016/0020-0190(85)90078-X
Validation of Asynchronous Circuit Specifications Using IF/CADP, Proceedings of the International Conference on Very Large Scale Integration of System-on-Chip VLSI-SoC 2003, pp.86-91, 2003. ,
DOI : 10.1007/0-387-33403-3_6
URL : https://hal.archives-ouvertes.fr/hal-00107431
CADP??2006: A Toolbox for the Construction and Analysis of Distributed Processes, Proceedings of the 19th International Conference on Computer Aided Verification CAV, pp.158-163, 2007. ,
DOI : 10.1007/978-3-540-73368-3_18
URL : https://hal.archives-ouvertes.fr/inria-00189021
LOTOS ? a formal description technique based on the temporal ordering of observational behaviour, International Organization for Standardization ? Information Processing Systems ? Open Systems Interconnection, 1989. ,
From hardware processes to asynchronous circuits via Petri nets: an application to arbiter design, Proceedings of the Workshop on Token Based Computing TOBACO'04, 2004. ,
URL : https://hal.archives-ouvertes.fr/hal-01392589
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63, 2005. ,
DOI : 10.1109/ASYNC.2005.10
Translating Hardware Process Algebras into Standard Process Algebras: Illustration with CHP and LOTOS, Proceedings of the 5th International Conference on Integrated Formal Methods IFM'2005, pp.287-306, 2005. ,
DOI : 10.1007/11589976_17
A fully abstract model for concurrent constraint programming, Proceedings of the International Joint Conference on Theory and Practice of Software Development TAPSOFT'91 Colloquium on Trees in Algebra and Programming CAAP'91, pp.296-319, 1991. ,
On concurrent functional-logic programming, Thèse de doctorat, Institut National Polytechnique de Grenoble, 2002. ,
Branching-time and abstraction in bisimulation semantics (extended abstract), CS R8911, proc. IFIP 11th World Computer Congress, p.1989, 1989. ,
Compilation and verification of LOTOS specifications, Proceedings of the 10th International Symposium on Protocol Specification, Testing and Verification, pp.379-394, 1990. ,
A Calculus of Communicating Systems, Lecture Notes in Computer Science, vol.92, 1980. ,
DOI : 10.1007/3-540-10235-3
Fundamentals of Algebraic Specification 1 ? Equations and Initial Semantics, EATCS Monographs on Theoretical Computer Science, vol.6, 1985. ,
Introduction to the ISO specification language LOTOS, Computer Networks and ISDN Systems, vol.14, issue.1, pp.25-59, 1988. ,
DOI : 10.1016/0169-7552(87)90085-7
State space reduction for process algebra specifications, Theoretical Computer Science, vol.351, issue.2, pp.131-145, 2006. ,
DOI : 10.1016/j.tcs.2005.09.064
State Space Reduction Using Partial ??-Confluence, Proceedings of the 25th International Symposium on Mathematical Foundations of Computer Science MFCS'2000, pp.383-393, 2000. ,
DOI : 10.1007/3-540-44612-5_34
A Graphical Parallel Composition Operator for Process Algebras, Proceedings of the Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols, and Protocol Specification, Testing, and Verification FORTE/PSTV'99, pp.185-202, 1999. ,
DOI : 10.1007/978-0-387-35578-8_11
BISIMULATOR: A Modular Tool for On-the-Fly Equivalence Checking, Proceedings of the 11th International Conference on Tools and Algorithms for the Construction and Analysis of Systems TACAS'2005, pp.581-585, 2005. ,
DOI : 10.1007/978-3-540-31980-1_42
URL : https://hal.archives-ouvertes.fr/hal-00685325
Enhancements to LOTOS (E-LOTOS), International Standard 15437, International Organization for Standardization ? Information Technology, 2001. ,
Compiler Construction Using LOTOS NT, Proceedings of the 11th International Conference on Compiler Construction CC 2002, pp.9-13, 2002. ,
DOI : 10.1007/3-540-45937-5_3
Compositional Verification Using SVL Scripts, Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems TACAS'2002, pp.465-469, 2002. ,
DOI : 10.1007/3-540-46002-0_33
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06), pp.172-181, 2006. ,
DOI : 10.1109/ASYNC.2006.16
FAUST : On-chip distributed architecture for a 4G baseband modem SoC, Proceedings of Design and Reuse IP-SOC'05 (France), pp.51-55, 2005. ,
SVL: A Scripting Language for Compositional Verification, Proceedings of the 21st IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems FORTE'2001, pp.377-392, 2001. ,
DOI : 10.1007/0-306-47003-9_24
URL : https://hal.archives-ouvertes.fr/inria-00072396
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), pp.73-82, 2007. ,
DOI : 10.1109/ASYNC.2007.18
Handshake Circuits: An Asynchronous Architecture for VLSI Programming, of International Series on Parallel Computation, 1993. ,
DOI : 10.1017/CBO9780511585777
Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware, Proceedings of the 4th International Workshop on Automated Verification of Critical Systems AVoCS'04, pp.231-246, 2004. ,
DOI : 10.1016/j.entcs.2005.04.014
Analyzing and verifying locally clocked circuits with the concurrency workbench, Proceedings. Fifth Great Lakes Symposium on VLSI, pp.144-147, 1995. ,
DOI : 10.1109/GLSV.1995.516041
SPIN as a hardware design tool, Proceedings of the First SPIN Workshop SPIN 1995, 1995. ,
The verification of asynchronous circuits using CCS, 1997. ,
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench, Information Processing Letters, vol.89, issue.6, pp.293-296, 2004. ,
DOI : 10.1016/j.ipl.2003.12.007
Verifying and Testing Asynchronous Circuits Using Lotos, Proceedings of the Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols, and Protocol Specification, Testing, and Verification FORTE, pp.267-283, 2000. ,
DOI : 10.1007/978-0-387-35533-7_17
CADP-based verification of asynchronous circuits, 2001. ,
Verification of Systems and Circuits Using LOTOS, Petri Nets, and CCS, Parallel and Distributed Computing, 2008. ,
On process-algebraic verification of asynchronous circuits, Sixth International Conference on Application of Concurrency to System Design (ACSD'06), pp.37-46, 2006. ,
DOI : 10.1109/ACSD.2006.16
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07), pp.83-94, 2007. ,
DOI : 10.1109/ASYNC.2007.19
An exercise in the automatic verification of asynchronous designs, Formal Methods in System Design, vol.86, issue.1, pp.213-242, 1994. ,
DOI : 10.1007/BF01384047
Property verification of asynchronous systems, Innovations in Systems and Software Engineering, vol.1, issue.1, pp.25-40, 2005. ,
DOI : 10.1007/s11334-005-0002-4