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Low Power Multistandard Simultaneous Reception Architecture
Abstract : In this paper, we address the architecture of multistandard simultaneous reception receivers and we aim at improving both the complexity and the power consumption of the analog front-end. To this end we propose an architecture using the double orthogonal translation technique in order to multiplex two received signals. A study case concerning the simultaneous reception of 802.11g and UMTS signals is developed in this article.
Cited literature [5 references]
https://hal.inria.fr/inria-00412028
Contributor : Guillaume Villemaud <>
Submitted on : Friday, November 27, 2009 - 10:32:41 AM
Last modification on : Wednesday, June 2, 2021 - 11:02:08 AM
Long-term archiving on: : Tuesday, June 15, 2010 - 9:12:46 PM
Contributor : Guillaume Villemaud <>
Submitted on : Friday, November 27, 2009 - 10:32:41 AM
Last modification on : Wednesday, June 2, 2021 - 11:02:08 AM
Long-term archiving on: : Tuesday, June 15, 2010 - 9:12:46 PM
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