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Conference papers

Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures

Cédric Augonnet 1, 2 Samuel Thibault 1, 2 Raymond Namyst 1, 2
2 RUNTIME - Efficient runtime systems for parallel architectures
Inria Bordeaux - Sud-Ouest, UB - Université de Bordeaux, CNRS - Centre National de la Recherche Scientifique : UMR5800
Abstract : Multicore architectures featuring specialized accelerators are getting an increasing amount of attention, and this success will probably influence the design of future High Performance Computing hardware. Unfortunately, programmers are actually having a hard time trying to exploit all these heterogeneous computing units efficiently, and most existing efforts simply focus on providing tools to offload some computations on available accelerators. Recently, some runtime systems have been designed that exploit the idea of scheduling -- as opposed to offloading -- parallel tasks over the whole set of heterogeneous computing units. Scheduling tasks over heterogeneous platforms makes it necessary to use accurate prediction models in order to assign each task to its most adequate computing unit. A deep knowledge of the application is usually required to model per-task performance models, based on the algorithmic complexity of the underlying numeric kernel. We present an alternate, auto-tuning performance prediction approach based on performance history tables dynamically built during the application run. This approach does not require that the programmer provides some specific information. We show that, thanks to the use of a carefully chosen hash-function, our approach quickly achieves accurate performance estimations automatically. Our approach even outperforms regular algorithmic performance models with several linear algebra numerical kernels.
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Submitted on : Thursday, October 1, 2009 - 4:32:12 PM
Last modification on : Monday, December 20, 2021 - 4:50:10 PM
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Cédric Augonnet, Samuel Thibault, Raymond Namyst. Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures. 3rd Workshop on Highly Parallel Processing on a Chip (HPPC 2009), Aug 2009, Delft, Netherlands. ⟨inria-00421333⟩



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