E. Hokenek, R. K. Montoye, and P. W. Cook, Second-generation RISC floating point with multiply-add fused, IEEE Journal of Solid-State Circuits, vol.25, issue.5, pp.1207-1213, 1990.
DOI : 10.1109/4.62143

R. K. Montoye, E. Hokonek, and S. L. Runyan, Design of the IBM RISC System/6000 floating-point execution unit, IBM Journal of Research and Development, vol.34, issue.1, pp.59-70, 1990.
DOI : 10.1147/rd.341.0059

P. W. Markstein, Computation of elementary functions on the IBM RISC System/6000 processor, IBM Journal of Research and Development, vol.34, issue.1, pp.111-119, 1990.
DOI : 10.1147/rd.341.0111

J. Muller, N. Brisebarre, F. De-dinechin, C. Jeannerod, V. Lefèvre et al., Handbook of Floating-Point Arithmetic, 2009.
DOI : 10.1007/978-0-8176-4705-6
URL : https://hal.archives-ouvertes.fr/ensl-00379167

R. Li, S. Boldo, and M. Daumas, Theorems on efficient argument reductions, 16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings., pp.129-136, 2003.
DOI : 10.1109/ARITH.2003.1207670
URL : https://hal.archives-ouvertes.fr/hal-00156244

R. M. Jessani and C. H. Olson, The floating-point unit of the PowerPC 603e microprocessor, IBM Journal of Research and Development, vol.40, issue.5, pp.559-566, 1996.
DOI : 10.1147/rd.405.0559

A. Kumar, The HP PA-8000 RISC CPU, IEEE Micro, vol.17, issue.2, pp.27-32, 1997.
DOI : 10.1109/40.592310

M. Cornea, J. Harrison, and P. T. Tang, Scientific Computing on Itanium R -based Systems, 2002.

E. Quinnell, E. E. Swartzlander, and C. Lemonds, Floating-Point Fused Multiply-Add Architectures, 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, pp.331-337, 2007.
DOI : 10.1109/ACSSC.2007.4487224
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.132.1908

O. Møller, Quasi double-precision in floating point addition, BIT, vol.7, issue.6, pp.37-50, 1965.
DOI : 10.1007/BF01975722

D. Knuth, The Art of Computer Programming, 1998.

T. J. Dekker, A floating-point technique for extending the available precision, Numerische Mathematik, vol.5, issue.3, pp.224-242, 1971.
DOI : 10.1007/BF01397083

S. Boldo and M. Daumas, Representable correcting terms for possibly underflowing floating point operations, 16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings., pp.79-86, 2003.
DOI : 10.1109/ARITH.2003.1207663

S. Boldo, Pitfalls of a Full Floating-Point Proof: Example on the Formal Proof of the Veltkamp/Dekker Algorithms, Proceedings of the 3rd International Joint Conference on Automated Reasoning, ser. Lecture Notes in Computer, pp.52-66, 2006.
DOI : 10.1007/11814771_6

S. Boldo and J. Muller, Some Functions Computable with a Fused-Mac, 17th IEEE Symposium on Computer Arithmetic (ARITH'05), 2005.
DOI : 10.1109/ARITH.2005.39
URL : https://hal.archives-ouvertes.fr/inria-00000895

N. Louvet, Algorithmes compensés en arithmétique flottante: Précision, validation, performances, 2007.

T. Ogita, S. M. Rump, and S. Oishi, Accurate Sum and Dot Product, SIAM Journal on Scientific Computing, vol.26, issue.6, pp.1955-1988, 2005.
DOI : 10.1137/030601818
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.2.1547

S. Boldo, M. Daumas, C. Moreau-finot, and L. Théry, Computer validated proofs of a toolset for adaptable arithmetic, École Normale Supérieure de Lyon, 2001.
URL : https://hal.archives-ouvertes.fr/hal-00018530