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Reconfigurable SWP Operator for Multimedia Processing

Shafqat Khan 1 Emmanuel Casseau 1 Daniel Menard 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : For performance enhancement, reconfigurable processors have to overcome the overheads of reconfigurations such as the complexity of the interconnection network and reconfiguration time. In processors dealing with multimedia applications these overheads can be reduced by providing the reconfigurability inside the processing units rather than at interconnection level. Due to the low precision data nature of multimedia applications, reconfiguration at operator level also provides additional speedup through parallel execution of low precision data. In this paper a pipelined architecture of a reconfigurable coarse grain subword parallel (SWP) operator is presented for multimedia applications. This operator not only eliminates the need of reconfiguration time but also provides the reconfigurability at both data size level (different pixel data sizes) and at operation level (different multimedia oriented operations). This ensures a better utilization of the processor resources and reduces the reconfiguration overheads significantly.
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https://hal.inria.fr/inria-00432572
Contributor : Daniel Menard Connect in order to contact the contributor
Submitted on : Monday, November 16, 2009 - 4:23:08 PM
Last modification on : Thursday, January 20, 2022 - 4:20:18 PM

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CNRS | INRIA | IRISA | UNIV-RENNES1 | IRISA-D3 | INRIA2 | UR1-MATH-STIC | UR1-UFR-ISTIC | UNIV-RENNES | INSTITUT-TELECOM | INSA-RENNES | EC-PARIS | UR1-MATH-NUM

Citation

Shafqat Khan, Emmanuel Casseau, Daniel Menard. Reconfigurable SWP Operator for Multimedia Processing. ASAP 2009 - 20th IEEE International Conference on Application-Specific Systems Architectures and Processors, Jul 2009, Boston, United States. pp.199-202, ⟨10.1109/ASAP.2009.13⟩. ⟨inria-00432572⟩

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