A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems

Abstract : The problem of converting floating point algorithms to implementation friendly fixed point formats is a formidable challenge. This problem is often solved as an optimization problem where the precision is traded to gain in the implementation cost. The complexity of the problem is known to grow exponentially with more optimizable variables. This paper proposes a divide and conquer technique to solve the growing size of the problem. The approach in this technique is original in the sense that it is formulated from a designers perspective rather than merely attempting to divide and conquer at the algorithmic level. This paper introduces the single noise source model based on which the proposed technique is built. A mixed approach for error propagation is also explained keeping in view of the elements in the circuit that cannot be handled analytically. A W-CDMA RAKE receiver implementation is analysed using this technique. The optimal solution is arrived at with in a span of few iterations.
Type de document :
Communication dans un congrès
23rd International Conference on VLSI Design, 2010. Proceedings, Bangalore, India, Jan 2010, Bangalore, India. 2010
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https://hal.inria.fr/inria-00432590
Contributeur : Daniel Menard <>
Soumis le : lundi 16 novembre 2009 - 16:38:51
Dernière modification le : mercredi 11 avril 2018 - 01:57:25

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  • HAL Id : inria-00432590, version 1

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Karthick Parashar, Romuald Rocher, Daniel Menard, Olivier Sentieys. A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. 23rd International Conference on VLSI Design, 2010. Proceedings, Bangalore, India, Jan 2010, Bangalore, India. 2010. 〈inria-00432590〉

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